CPU chip

The platform consists of AMBA on-chip bus models, RISC CPU model and memory module.

平台主要包括基于AMBA规范的总线模型、RISC CPU模型和存储器模型。通过GUI可以进行设计仿真。

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Principal and Subordinate Navigation Computer with Dual CPU Based on DSP and AVR Single-chip Processor

基于DSP和AVR单片机的主从式双CPU导航计算机

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Importing the different virtual CPU chip, can imitate different type experiment on the same virtual platform;

通过引入不同的虚拟CPU芯片，可在同一虚拟平台上实现不同类型的微型机硬件虚拟实验。

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Use the DSP, extended memory SDRAM and the boot load flash chip, realize a image processing and CPU system.

通过DSP、外扩SDRAM和上电加载FLASH芯片，构建了一个图像处理和中央控制系统。

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Based on the principle of the time base error producing, using frame memory, PAL coded chip, CPU, FPGA control logic, the video time base correct circuit is realized.

在分析时基误差产生原理的基础上，利用帧存和PAL（逐行倒相）编解码芯片及CPU和FPGA（现场可编程门阵列）控制逻辑设计实现了视频时基校正电路。

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A Functional Verification Scheme for a DSP& CPU Chip Based on PC and Data Acquisition System

基于PC与数据采集系统的DSP&CPU芯片功能验证方案

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Design Verification via Simulation: Techniques and Their Application in a General-purposed CPU Chip

通用CPU设计中的模拟验证技术及应用

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Design and Implementation of a CPU Chip Hardware Test and Debug Platform

一种CPU芯片硬件验证调试平台的设计与实现

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The floating-point unit integrated into the CPU chip has signaled an error condition, such as numeric overflow or division by0.

集成到CPU芯片的浮点数单元产生一个错误条件，比如数字溢出或者除0。

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In this dissertation, some approaches are given to optimize the memory usage of SOC. Since the MPEG-2 decoding chip is a SOC, 32-bits embedded RISC CPU core is used to decode the AC3 and TS bit stream.

论文设计的MPEG-2系统集成解码芯片是一个SoC，该SoC采用32位嵌入式RISC CPU核Virgo进行音频AC3和TS流解码的计算任务，并承担SoC的管理；

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Intelligent Fan Control Device Based on High-speed 16-bit CPU Chip Switchgear

基于高速16位CPU芯片的开关柜风扇智能化控制装置

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